URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 132

Rev	Log message	Author	Age	Path
132	Added test program for testing uart.	jlechner	6361d 19h	/
131	Changed high active resets to low active ones.	jlechner	6361d 19h	/
130	Removed obsolete line	jlechner	6361d 19h	/
129	Sample assembler program for accessing uart	jlechner	6361d 19h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6361d 20h	/
127	Changed high active resets to low active ones.	jlechner	6361d 20h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6362d 02h	/
125	Fixed vhdl bugs	trinklhar	6362d 02h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6362d 02h	/
123	Removed UART again	trinklhar	6362d 03h	/
122	Removed UART again again	trinklhar	6362d 03h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6362d 03h	/
120	Added UART module to memory entity	trinklhar	6362d 03h	/
119	Uart wieder ausgebaut	trinklhar	6362d 22h	/
118	insert Uart address constant	trinklhar	6362d 22h	/
117	Uart im mem_stage	trinklhar	6362d 22h	/
116	writes to uart when write to reg 0	trinklhar	6364d 04h	/
115	* empty log message *	trinklhar	6364d 18h	/
114	Uart 0.3	trinklhar	6365d 23h	/
113	Uart reset funkt	trinklhar	6366d 00h	/