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Rev Log message Author Age Path
132 Added test program for testing uart. jlechner 6362d 01h /
131 Changed high active resets to low active ones. jlechner 6362d 01h /
130 Removed obsolete line jlechner 6362d 01h /
129 Sample assembler program for accessing uart jlechner 6362d 01h /
128 Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles
if ordinary memory data or data of an extension module have to be passed on.
jlechner 6362d 02h /
127 Changed high active resets to low active ones. jlechner 6362d 02h /
126 Added constant for cpu frequency (needed for UART) trinklhar 6362d 08h /
125 Fixed vhdl bugs trinklhar 6362d 08h /
124 Assigned UART signals to ports on top-level entity trinklhar 6362d 08h /
123 Removed UART again trinklhar 6362d 09h /
122 Removed UART again again trinklhar 6362d 09h /
121 Added address constants for uart access (memory mapped I/O) trinklhar 6362d 09h /
120 Added UART module to memory entity trinklhar 6362d 09h /
119 Uart wieder ausgebaut trinklhar 6363d 04h /
118 insert Uart address constant trinklhar 6363d 04h /
117 Uart im mem_stage trinklhar 6363d 04h /
116 writes to uart when write to reg 0 trinklhar 6364d 11h /
115 *** empty log message *** trinklhar 6365d 01h /
114 Uart 0.3 trinklhar 6366d 05h /
113 Uart reset funkt trinklhar 6366d 06h /

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