URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 138

Rev	Log message	Author	Age	Path
138	- Fixed binary to VHDL converter.	cwalter	6360d 08h	/
137	- Added binary to VHDL converter.	cwalter	6360d 09h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6360d 09h	/
135	uart_address_0 was a latch -> changed	ustadler	6361d 05h	/
134	Added second test program for testing uart.	jlechner	6361d 05h	/
133	- Fixed bug with ST opcodes.	cwalter	6361d 07h	/
132	Added test program for testing uart.	jlechner	6361d 07h	/
131	Changed high active resets to low active ones.	jlechner	6361d 07h	/
130	Removed obsolete line	jlechner	6361d 07h	/
129	Sample assembler program for accessing uart	jlechner	6361d 07h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6361d 07h	/
127	Changed high active resets to low active ones.	jlechner	6361d 07h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6361d 14h	/
125	Fixed vhdl bugs	trinklhar	6361d 14h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6361d 14h	/
123	Removed UART again	trinklhar	6361d 15h	/
122	Removed UART again again	trinklhar	6361d 15h	/
121	Added address constants for uart access (memory mapped I/O)	trinklhar	6361d 15h	/
120	Added UART module to memory entity	trinklhar	6361d 15h	/
119	Uart wieder ausgebaut	trinklhar	6362d 10h	/