URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 141

Rev	Log message	Author	Age	Path
141	- Added delay between characters.	cwalter	6352d 21h	/
140	- Test bench for RISE with UART.	cwalter	6352d 21h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6352d 21h	/
138	- Fixed binary to VHDL converter.	cwalter	6352d 21h	/
137	- Added binary to VHDL converter.	cwalter	6352d 22h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6352d 22h	/
135	uart_address_0 was a latch -> changed	ustadler	6353d 18h	/
134	Added second test program for testing uart.	jlechner	6353d 18h	/
133	- Fixed bug with ST opcodes.	cwalter	6353d 20h	/
132	Added test program for testing uart.	jlechner	6353d 20h	/
131	Changed high active resets to low active ones.	jlechner	6353d 20h	/
130	Removed obsolete line	jlechner	6353d 20h	/
129	Sample assembler program for accessing uart	jlechner	6353d 20h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6353d 21h	/
127	Changed high active resets to low active ones.	jlechner	6353d 21h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6354d 03h	/
125	Fixed vhdl bugs	trinklhar	6354d 03h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6354d 03h	/
123	Removed UART again	trinklhar	6354d 04h	/
122	Removed UART again again	trinklhar	6354d 04h	/