URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 142

Rev	Log message	Author	Age	Path
142	- Added gap between characters sent and changed last character to CR.	cwalter	6361d 00h	/
141	- Added delay between characters.	cwalter	6361d 00h	/
140	- Test bench for RISE with UART.	cwalter	6361d 00h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6361d 01h	/
138	- Fixed binary to VHDL converter.	cwalter	6361d 01h	/
137	- Added binary to VHDL converter.	cwalter	6361d 02h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6361d 02h	/
135	uart_address_0 was a latch -> changed	ustadler	6361d 22h	/
134	Added second test program for testing uart.	jlechner	6361d 22h	/
133	- Fixed bug with ST opcodes.	cwalter	6362d 00h	/
132	Added test program for testing uart.	jlechner	6362d 00h	/
131	Changed high active resets to low active ones.	jlechner	6362d 00h	/
130	Removed obsolete line	jlechner	6362d 00h	/
129	Sample assembler program for accessing uart	jlechner	6362d 00h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6362d 00h	/
127	Changed high active resets to low active ones.	jlechner	6362d 00h	/
126	Added constant for cpu frequency (needed for UART)	trinklhar	6362d 07h	/
125	Fixed vhdl bugs	trinklhar	6362d 07h	/
124	Assigned UART signals to ports on top-level entity	trinklhar	6362d 07h	/
123	Removed UART again	trinklhar	6362d 08h	/