URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] - Rev 146

Rev	Log message	Author	Age	Path
146	- Changed to compile UART example.	cwalter	6374d 22h	/
145	- Added more VHDL files to project.	cwalter	6374d 22h	/
144	- IF stage now uses autogenerated VHDL files.	cwalter	6374d 22h	/
143	- Added more complex UART example.	cwalter	6374d 22h	/
142	- Added gap between characters sent and changed last character to CR.	cwalter	6374d 22h	/
141	- Added delay between characters.	cwalter	6374d 23h	/
140	- Test bench for RISE with UART.	cwalter	6374d 23h	/
139	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6375d 00h	/
138	- Fixed binary to VHDL converter.	cwalter	6375d 00h	/
137	- Added binary to VHDL converter.	cwalter	6375d 00h	/
136	- Added makefile example to improve design flow. - Added subroutine example.	cwalter	6375d 00h	/
135	uart_address_0 was a latch -> changed	ustadler	6375d 20h	/
134	Added second test program for testing uart.	jlechner	6375d 21h	/
133	- Fixed bug with ST opcodes.	cwalter	6375d 22h	/
132	Added test program for testing uart.	jlechner	6375d 23h	/
131	Changed high active resets to low active ones.	jlechner	6375d 23h	/
130	Removed obsolete line	jlechner	6375d 23h	/
129	Sample assembler program for accessing uart	jlechner	6375d 23h	/
128	Added multiplexer for output data. This mutliplexer decides on the adress of the last cycles if ordinary memory data or data of an extension module have to be passed on.	jlechner	6375d 23h	/
127	Changed high active resets to low active ones.	jlechner	6375d 23h	/