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Rev Log message Author Age Path
15 - Added second register locking port reg_lock1.
- Added function to check if the instruction modifies the SR register.
- Fetch of SR now checks if the SR is modified and if yes the SR register
is marked as locked.
- Stall signal for pipeline is now generated correctly.
- Stall input is now checked. If asserted the current output values are hold
until the stall signal is deasserted.		 cwalter 6395d 17h /
14 - Renamed clear/set_reg_lock to clear/set_reg_lock0.
- Added second register locking port reg_lock1.		 cwalter 6395d 17h /
13 - Testbench now implements a simple register file.
- Added new tests for OPCODE_LD_DISP, OPCODE_LD_DISP_MS
OPCODE_LD_REG.		 cwalter 6398d 15h /
12 - Added constant definitions for SR, PC and LR register. cwalter 6398d 15h /
11 - Added checks to test if a register has been locked. If it is locked and
used in the decoded instruction the stall_out signal is asserted.
- Added missing signals to process sensitivity list.
- Fixed bug in rY decoding where the value of rZ was used.
- Implemented opcode_modifies_rx.		 cwalter 6398d 15h /
10 - added testbench for load immediate and load immediate with high byte. cwalter 6400d 18h /
9 - added support for immediate value decoding.
- opcode extender now works correctly for load immediate. needed special
handling for the high byte bit.
- conditional decoder needed special handling for high byte bit.		 cwalter 6400d 18h /
8 Implementation of execute stage and register lock unit. Some changes im RISE package. jlechner 6400d 22h /
7 - initial version of instruction decode stage testbench. cwalter 6419d 15h /
6 - applied VHDL source code indenter. cwalter 6419d 15h /
5 - correct register address width is 4 bit and not 5 bit.
- added constants for OPCODES, COND and SR.		 cwalter 6419d 15h /
4 - added decode for rX, rY, rZ.
- added decode for opcodes.		 cwalter 6419d 15h /
3 Add pipeline design documents jlechner 6425d 18h /
2 Initial commit of project jlechner 6425d 18h /
1 Standard project directories initialized by cvs2svn. 6425d 18h /

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