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Rev	Log message	Author	Age	Path
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6417d 23h	/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6418d 01h	/
19	Version 1.2 der register file	ustadler	6418d 08h	/
18	Update of pipeline schematics: - Fixed errors - Changed names of some signals so they are equal with VHDL code - Added second register lock port	jlechner	6419d 03h	/
17	- Added new tests for pipeline stall signal. - Added tests for register locking. - Added tests for OPCODE_ST_DISP, OPCODE_ADD, OPCODE_ADD_IMM OPCODE_SUB_IMM, OPCODE_NEG, OPCODE_ARS and OPCODE_ALS.	cwalter	6421d 01h	/
16	- Added second register locking port reg_lock1 to RLU.	cwalter	6421d 01h	/
15	- Added second register locking port reg_lock1. - Added function to check if the instruction modifies the SR register. - Fetch of SR now checks if the SR is modified and if yes the SR register is marked as locked. - Stall signal for pipeline is now generated correctly. - Stall input is now checked. If asserted the current output values are hold until the stall signal is deasserted.	cwalter	6421d 01h	/
14	- Renamed clear/set_reg_lock to clear/set_reg_lock0. - Added second register locking port reg_lock1.	cwalter	6421d 01h	/
13	- Testbench now implements a simple register file. - Added new tests for OPCODE_LD_DISP, OPCODE_LD_DISP_MS OPCODE_LD_REG.	cwalter	6423d 23h	/
12	- Added constant definitions for SR, PC and LR register.	cwalter	6423d 23h	/
11	- Added checks to test if a register has been locked. If it is locked and used in the decoded instruction the stall_out signal is asserted. - Added missing signals to process sensitivity list. - Fixed bug in rY decoding where the value of rZ was used. - Implemented opcode_modifies_rx.	cwalter	6423d 23h	/
10	- added testbench for load immediate and load immediate with high byte.	cwalter	6426d 02h	/
9	- added support for immediate value decoding. - opcode extender now works correctly for load immediate. needed special handling for the high byte bit. - conditional decoder needed special handling for high byte bit.	cwalter	6426d 02h	/
8	Implementation of execute stage and register lock unit. Some changes im RISE package.	jlechner	6426d 06h	/
7	- initial version of instruction decode stage testbench.	cwalter	6444d 23h	/
6	- applied VHDL source code indenter.	cwalter	6444d 23h	/
5	- correct register address width is 4 bit and not 5 bit. - added constants for OPCODES, COND and SR.	cwalter	6444d 23h	/
4	- added decode for rX, rY, rZ. - added decode for opcodes.	cwalter	6444d 23h	/
3	Add pipeline design documents	jlechner	6451d 02h	/
2	Initial commit of project	jlechner	6451d 02h	/

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