URL https://opencores.org/ocsvn/rise/rise/trunk

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Rev	Log message	Author	Age	Path
37	Applied VHDL indent.	jlechner	6388d 10h	/
36	- Testbench for RISE.	cwalter	6388d 10h	/
35	- Testbench for register file.	cwalter	6388d 10h	/
34	- Filex have been renamed to have tb prefix.	cwalter	6388d 10h	/
33	- Fixed process sensitivity list.	cwalter	6388d 11h	/
32	- When this stage asserts stall_out it must clear the input for the next stage. - Fixed process sensitivity list.	cwalter	6388d 11h	/
31	- Added PC_RESET_VECTOR constant.	cwalter	6388d 12h	/
30	- Top level testbench for RISE.	cwalter	6388d 12h	/
29	- Initial version of IF stage with dummy instructions.	cwalter	6388d 12h	/
28	Added new register write enable signals.	jlechner	6390d 06h	/
27	Added new register write enable signals to component instantiation of register_file and wb_stage.	jlechner	6390d 06h	/
26	Applied VHDL indent.	jlechner	6390d 06h	/
25	netlist file for the memories is needed for IMEM and DMEM	ustadler	6391d 06h	/
24	4k Data Instruction for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6391d 06h	/
23	4k Data Memory for Spartan 3 (Block RAM) Added write enable to the entity	ustadler	6391d 06h	/
22	testbench für die register file	ustadler	6391d 19h	/
21	überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt	ustadler	6392d 07h	/
20	- Fixed bug where SR fetch code locked wrong register.	cwalter	6392d 09h	/
19	Version 1.2 der register file	ustadler	6392d 16h	/
18	Update of pipeline schematics: - Fixed errors - Changed names of some signals so they are equal with VHDL code - Added second register lock port	jlechner	6393d 11h	/

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[/] - Rev 37

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