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43 Correct implementation of necessary unlocking signals that are conncted to register locking unit. jlechner 6414d 08h /
42 Modified input signals for register locking (testbench modifications):
Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle
there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).
jlechner 6414d 08h /
41 Modified input signals for register locking:
Since id-stage and write-back-stage may have to lock or unlock two registers in one cycle
there are now seperate locking and unlocking adress inputs (two ports for locking/ two for unlocking).
jlechner 6414d 08h /
40 - Added seperate memory output vector to MEM_WB_REGISTER.
- Added status register to MEM_WB_REGISTER.
jlechner 6414d 08h /
39 - Added wr_enable signals for imem and dmem
- Changed signals for register lock unit (this concerns id-stage and write-back-stage)
jlechner 6414d 08h /
38 Memory output signal is now passed on asynchronously to write back stage. jlechner 6414d 08h /
37 Applied VHDL indent. jlechner 6414d 08h /
36 - Testbench for RISE. cwalter 6414d 09h /
35 - Testbench for register file. cwalter 6414d 09h /
34 - Filex have been renamed to have tb prefix. cwalter 6414d 09h /
33 - Fixed process sensitivity list. cwalter 6414d 09h /
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.
cwalter 6414d 09h /
31 - Added PC_RESET_VECTOR constant. cwalter 6414d 11h /
30 - Top level testbench for RISE. cwalter 6414d 11h /
29 - Initial version of IF stage with dummy instructions. cwalter 6414d 11h /
28 Added new register write enable signals. jlechner 6416d 04h /
27 Added new register write enable signals to component instantiation of register_file and wb_stage. jlechner 6416d 04h /
26 Applied VHDL indent. jlechner 6416d 04h /
25 netlist file for the memories
is needed for IMEM and DMEM
ustadler 6417d 04h /
24 4k Data Instruction for Spartan 3 (Block RAM)
Added write enable to the entity
ustadler 6417d 04h /

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