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Rev Log message Author Age Path
10 Implemented asynchronous mode and RX clock regeneration.
NOT TESTED !!!
akram.mashni 4964d 18h /
9 Updated change log. akram.mashni 5002d 09h /
8 Added Recommended Tools akram.mashni 5002d 09h /
7 Implemented PARITY (not tested!). akram.mashni 5003d 20h /
6 Fixed/improved header.
Changed SPACEs to TABs.
akram.mashni 5005d 02h /
5 Added comments to port map. akram.mashni 5012d 06h /
4 Added "Change Log".
Added "About"
akram.mashni 5012d 07h /
3 Added main file.
Fisrt commit.
Tested in the following conditions:
- Baud rate: 9600 bps.
- Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent)
- Main clock 50 MHz
akram.mashni 5012d 07h /
2 Initial Commit luciorp 5068d 20h /
1 The project and the structure was created root 5096d 16h /

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