URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

Subversion Repositories rs232_interface

[/] - Rev 17

Rev	Log message	Author	Age	Path
17	First commit of uart test bench. WARNING: Not yet finished! Commited for back up.	akram.mashni	4790d 01h	/
16	Project's block diagram. It will be use in the datasheet. (Compression level 5 when export from .odg file).	akram.mashni	4891d 10h	/
15	Removed uncompressed image with big size.	akram.mashni	4891d 10h	/
14	Block diagram image of 2011-01-16 version. It will be use in the datasheet. (Compression level 5 when export from .odg file).	akram.mashni	4891d 10h	/
13	Initial commit of documentation. Created block diagram (OpenOffice Draw format).	akram.mashni	4891d 10h	/
12	Updated news of uart.vhd commit.	akram.mashni	4892d 13h	/
11	Moved debouncer to a new process. Fixed rx_clk_en generation. Fixed start of reception condition on rx FSM.	akram.mashni	4892d 13h	/
10	Implemented asynchronous mode and RX clock regeneration. NOT TESTED !!!	akram.mashni	4900d 07h	/
9	Updated change log.	akram.mashni	4937d 22h	/
8	Added Recommended Tools	akram.mashni	4937d 22h	/
7	Implemented PARITY (not tested!).	akram.mashni	4939d 09h	/
6	Fixed/improved header. Changed SPACEs to TABs.	akram.mashni	4940d 14h	/
5	Added comments to port map.	akram.mashni	4947d 19h	/
4	Added "Change Log". Added "About"	akram.mashni	4947d 19h	/
3	Added main file. Fisrt commit. Tested in the following conditions: - Baud rate: 9600 bps. - Implementation: Xilinx Spartan3e500 (Nexys2 Kit - Digilent) - Main clock 50 MHz	akram.mashni	4947d 20h	/
2	Initial Commit	luciorp	5004d 08h	/
1	The project and the structure was created	root	5032d 05h	/