URL https://opencores.org/ocsvn/rtf65002/rtf65002/trunk

Subversion Repositories rtf65002

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Rev	Log message	Author	Age	Path
22	- fix indirect load	robfinch	3912d 06h	/
21	- config processor mode on reset - D flag flags extended precision for add/sub - added software interrupt call facility - unimplmented opcode vectoring - bus error signal support - merge load states to reduce core size - zero out ir during interrupt	robfinch	3912d 12h	/
20	- greater separation of emulation and native mode in source code - fix instruction buffer fetch for non-cached accesses - fix the sta (d),y instruction	robfinch	3913d 18h	/
19	- added multibit shifts - added eight bit CMP instruction	robfinch	3914d 16h	/
18	- added shift instruction to assembler - fixed acouple of minor bugs	robfinch	3914d 16h	/
17	- updated docs	robfinch	3914d 16h	/
16	- tiny basic	robfinch	3915d 16h	/
15	- updates to assembler - interrupt support in bootrom.asm -	robfinch	3915d 16h	/
14	- updated docs	robfinch	3915d 16h	/
13	- fix overflow in immediate mode - fix bit instruction N,V setting - add vector base register, modified interrupt vectoring	robfinch	3915d 16h	/
12	- added LFSR and TICK count special registers - added MUL/DIV/MOD instructions	robfinch	3916d 17h	/
11	- added bootrom.asm - fixed bugs in assembler	robfinch	3918d 21h	/
10	- fix rind mode in 32 bit mode - fix flag update in 32 bit mode for RR instructions - initialize cache tags - added flag to disable ints until after sp load	robfinch	3918d 21h	/
9	updateing docs	robfinch	3919d 21h	/
8	updateing docs	robfinch	3919d 21h	/
7	updateing docs	robfinch	3919d 21h	/
6	setting up project	robfinch	3922d 05h	/
5	setting up project	robfinch	3922d 05h	/
4	setting up project	robfinch	3922d 05h	/
3	setting up project	robfinch	3922d 05h	/

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Subversion Repositories rtf65002

[/] - Rev 22

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