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Rev Log message Author Age Path
40 - sample files in assembler robfinch 3681d 20h /
39 - updated assembler plus sample files robfinch 3681d 20h /
38 - updated to support the 65c816 opcodes robfinch 3681d 20h /
37 - latest documentation robfinch 3830d 16h /
36 - missing TRB/TSB instructions in 32 bit mode added robfinch 3830d 16h /
35 - several bug fixes
- mul,mod,div immediates mode than 8 bits
- page two opcode fix on cache miss
- setting upper pc bits in emulation mode (store)		 robfinch 3877d 08h /
34 - latest bootrom.asm
- and assembler		 robfinch 3887d 22h /
33 - most recent docs robfinch 3887d 22h /
32 - many changes
- new instructions
- code reorganization		 robfinch 3887d 22h /
31 - miscellaneous updates
- unimplemented instruction vector
-		 robfinch 3897d 20h /
30 - added additional branches
- modified the pc increment
- modified interrupts, all vector through BRK
- registered some decodes
- added SUPPORT macros to allow core trimming		 robfinch 3897d 20h /
29 - updated assembler, increased instruction support robfinch 3903d 15h /
28 - updated bootrom, robfinch 3903d 15h /
27 - most recent doc robfinch 3904d 22h /
26 - latest bootrom.asm
- fixes to assembler		 robfinch 3904d 22h /
25 - add EXEC and ATNI instructions
- fix store byte zero page indexed
- fix break instruction		 robfinch 3904d 22h /
24 - fixes to assembler robfinch 3910d 20h /
23 - added subtract immediate from sp
- added stack relative addressing mode
- added move positive, move negative instructions
- fix: TSA instruction		 robfinch 3910d 20h /
22 - fix indirect load robfinch 3912d 10h /
21 - config processor mode on reset
- D flag flags extended precision for add/sub
- added software interrupt call facility
- unimplmented opcode vectoring
- bus error signal support
- merge load states to reduce core size
- zero out ir during interrupt		 robfinch 3912d 15h /

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