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Rev Log message Author Age Path
47 Updated with `define preprocessing for Xilinx XST synthesis fafa1971 6295d 16h /
46 Fresh version from OpenSPARC 1.4 and Icarus define preprocessing fafa1971 6295d 16h /
45 I'm going to remove original OpenSPARC 1.4 files so that I can insert again
the ones with Icarus Verilog preprocessor already applied by update_sparccore
(it seems that Xilinx's XST does NOT support defines at compile time)		 fafa1971 6295d 16h /
44 Embedded `defines into Verilog source since did not find command line option for XST fafa1971 6296d 15h /
43 Added welcome message as a remainder to set paths for tools!=IVerilog fafa1971 6296d 15h /
42 Added support for filelist for Xilinx ISE XST synthesis fafa1971 6296d 15h /
41 Added copy of empty modules upon original SPARC copies fafa1971 6296d 15h /
40 First version of synthesis script for Xilinx ISE XST fafa1971 6296d 15h /
39 Empty modules for cacheless Simply RISC S1 Core fafa1971 6296d 15h /
38 Changed to compile (for now) the boot code. fafa1971 6300d 14h /
37 Memory image coming from the new boot.s fafa1971 6300d 14h /
36 Working boot code!!! fafa1971 6300d 14h /
35 Fixed Assembly comments ("//" had to become "!!"). fafa1971 6300d 15h /
34 This file is useless. fafa1971 6309d 23h /
33 Added inclusion of defines.h in boot.s fafa1971 6310d 14h /
32 First version of cutdown boot code for SPARC V9. fafa1971 6310d 14h /
31 Removed list of formerly dirty signals, to improve waveforms readability. fafa1971 6310d 16h /
30 Added comment for 8 stores to Interrupt Queue Registers that have been removed. fafa1971 6310d 16h /
29 Removed closed bug from todolist. fafa1971 6310d 16h /
28 Before it was empty (getting NOPs by default), now it is the same as the one in
the official OpenSPARC T1 verification environment (mem_RED_EXT_SEC.image_ORIGINAL)
and I just had to remove 8 stores to Interrupt Queues Registers.		 fafa1971 6310d 16h /

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