URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

[/] - Rev 91

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Rev	Log message	Author	Age	Path
91	Filelists updated according to preprocessed files from OpenSPARC T1 1.6	fafa1971	5798d 04h	/
90	Added newer files from OpenSPARC T1 1.6 preprocessed with "update_sparccore -ee"	fafa1971	5798d 04h	/
89	Removed files originated from OpenSPARC T1 Design 1.5 preprocessed with "update_sparccore -me"	fafa1971	5798d 04h	/
88	After one year found time to translate Giovanni Di Blasi's comments to boot code!	fafa1971	5800d 06h	/
87	Corrected comment delimiter.	fafa1971	5926d 16h	/
86	Added 'lain.ux'-style checks for environment vars to be set (I lost data as well!!!).	fafa1971	5939d 11h	/
85	GREAT synthesis script!!! Performs all bottom-up synthesis without errors.	fafa1971	5941d 13h	/
84	Again, used module names instead than instance names in bottom-up synthesis approach.	fafa1971	5941d 16h	/
83	Decreased clock frequency from 250 to 200 MHz.	fafa1971	5948d 11h	/
82	DC synthesis script modified according to the fabolous manual (RTFM...).	fafa1971	5959d 11h	/
81	Sorry, I made a mistake in the waveform of the clock!	fafa1971	5959d 15h	/
80	Hyerarchical report_area.	fafa1971	5962d 11h	/
79	Relaxed timing, added flatten and hyerarchical report_area.	fafa1971	5962d 11h	/
78	Relaxed timing and added flatten command.	fafa1971	5962d 11h	/
77	Now includes comments (in Italian!)	fafa1971	6047d 09h	/
76	Changed again from DB export to DDC export	fafa1971	6062d 08h	/
75	Changed preprocessing for DC synthesis	fafa1971	6062d 12h	/
74	Updated filelists.	fafa1971	6062d 12h	/
73	New version of scripts for DC and to compile boot code	fafa1971	6062d 12h	/
72	Modified RAM address from 0x400C0 to 0x4C000	fafa1971	6068d 19h	/

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Subversion Repositories s1_core

[/] - Rev 91

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