URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 116

Rev	Log message	Author	Age	Path
116	Wishbone interface for sd core started	rkastl	4923d 14h	/
115	WbSlave: New header.	rkastl	4923d 14h	/
114	Read works with model too.	rkastl	4923d 14h	/
113	Read with single block works on cards, but not in simulation. SdData.sv sends data with one "XXXX" cycle right before the crc.	rkastl	4923d 14h	/
112	Save wide mode with out gHighSpeedMode = true	rkastl	4923d 14h	/
111	Sclk moved to neg. edge -> setup and hold times for fast mode are easier to reach. (only micro sd does not work in fast mode).	rkastl	4923d 14h	/
110	All except microsd work in highspeed mode.	rkastl	4923d 14h	/
109	Added a data ram.	rkastl	4923d 14h	/
108	Added a ram to the testbed	rkastl	4923d 14h	/
107	Forgot to add Counter in last commit.	rkastl	4923d 14h	/
106	Fixes #29: All cards respond, but they do not all work.	rkastl	4923d 14h	/
105	Changing speed works! refs #33	rkastl	4923d 14h	/
104	SdController: Configuration ready to switch to high speed, refs #33	rkastl	4923d 14h	/
103	SdController: Checking speed works	rkastl	4923d 14h	/
102	SdController: Enabling wide mode works, refs #33	rkastl	4923d 14h	/
101	Receiving response to ACMD51 works including data, refs #33.	rkastl	4923d 14h	/
100	SdController: Receiving data after ACMD51, but CRC is wrong	rkastl	4923d 14h	/
99	SdController: Checking bus width without receiving data response	rkastl	4923d 14h	/
98	SdController: Receive response to CMD7 (except when busy is activated)	rkastl	4923d 14h	/
97	SdController: CMD55 out of main state into Region	rkastl	4923d 14h	/