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Subversion Repositories sdhc-sc-core

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Rev	Log message	Author	Age	Path
137	Regression test suite: Removed unneeded testbenches from the makefile. Only complete reusable blocks are tested from now on.	rkastl	4923d 10h	/
136	SDHC: - SdData refactored to use a single counter - TestWbMaster added to TbdSd (not functional yet)	rkastl	4923d 10h	/
135	Multiple-Inclusion-Protection to SystemVerilog files added Stops using relative paths in `includes. instead +incdir has to be used.	rkastl	4923d 10h	/
134	SdData: Further refactoring.	rkastl	4923d 10h	/
133	SdData: Further refactoring	rkastl	4923d 10h	/
132	SdData: Refactoring, not done. Testbench works again, but does not really test anything.	rkastl	4923d 10h	/
131	SdClockMaster added to regression tests	rkastl	4923d 10h	/
130	SdClockMaster: Formal verification	rkastl	4923d 10h	/
129	SdClockMaster: Redesigned, not finished. Tb with PSL assertions.	rkastl	4923d 10h	/
128	Sim: Support for psl files added.	rkastl	4923d 10h	/
127	Thesis: Restructured SDHC chapter.	rkastl	4923d 10h	/
126	Read and Write works in simulation, needs verification. Synthesis works the same like before.	rkastl	4923d 10h	/
125	Write works in simulation	rkastl	4923d 10h	/
124	Write: SdClk is disabled, if no data is available.	rkastl	4923d 10h	/
123	Write: Must be able to halt SdClk, rest is done.	rkastl	4923d 10h	/
122	SdController: Initial read support	rkastl	4923d 13h	/
121	SdWbSlave inserted into SdTop. SdController does not use it yet.	rkastl	4923d 13h	/
120	SdWbSlave: ClassicRead and ClassicWrite work	rkastl	4923d 13h	/
119	SdWb: Synchronization of operation to SdController done, but needs testing.	rkastl	4923d 13h	/
118	EdgeDetector added.	rkastl	4923d 13h	/

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Subversion Repositories sdhc-sc-core

[/] - Rev 137

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