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Rev Log message Author Age Path
144 Simulation files for tbTbdSd created.

tbTbdSd is not done and TestWbMaster seems to be lost.		 rkastl 4999d 00h /
143 Ignore pattern:
+ work
+ modelsim.ini
+ vsim.wlf
+ transcript
+ cycloneii and altera_mf generated library folders		 rkastl 4999d 00h /
142 Thesis: PDF added to .gitignore rkastl 4999d 00h /
141 Added *.bak to ignore file. rkastl 4999d 00h /
140 Removed tbSdData-Bhv-ea.vhdl. Non-automated tb, tested in complete
verification tb anyway.		 rkastl 4999d 00h /
139 Removed Testbench for unitSdWbSlave. Again: weak tb and it´s tested in
the complete verification environment anyway.		 rkastl 4999d 00h /
138 Removed testbench for unitSdCmd because it was a weak testbench and the
functionality is tested in the SdVerificationTestbench anyway.		 rkastl 4999d 00h /
137 Regression test suite:

Removed unneeded testbenches from the makefile. Only complete reusable
blocks are tested from now on.		 rkastl 4999d 00h /
136 SDHC:
- SdData refactored to use a single counter
- TestWbMaster added to TbdSd (not functional yet)		 rkastl 4999d 00h /
135 Multiple-Inclusion-Protection to SystemVerilog files added
Stops using relative paths in `includes. instead +incdir has to be used.		 rkastl 4999d 00h /
134 SdData: Further refactoring. rkastl 4999d 00h /
133 SdData: Further refactoring rkastl 4999d 00h /
132 SdData: Refactoring, not done.
Testbench works again, but does not really test anything.		 rkastl 4999d 00h /
131 SdClockMaster added to regression tests rkastl 4999d 00h /
130 SdClockMaster: Formal verification rkastl 4999d 00h /
129 SdClockMaster: Redesigned, not finished. Tb with PSL assertions. rkastl 4999d 00h /
128 Sim: Support for psl files added. rkastl 4999d 00h /
127 Thesis: Restructured SDHC chapter. rkastl 4999d 00h /
126 Read and Write works in simulation, needs verification.
Synthesis works the same like before.		 rkastl 4999d 00h /
125 Write works in simulation rkastl 4999d 00h /

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