URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 180

Rev	Log message	Author	Age	Path
180	Moved WbClkDomain to its own unit. Refs #60.	rkastl	4897d 16h	/
179	Fixing build: Added library generation to Makefile.	rkastl	4897d 16h	/
178	Fixed regression: Testbenches did not support synchronous reset.	rkastl	4897d 16h	/
177	Split SdTop into SdClkDomain and SdTop. Refs #60.	rkastl	4897d 16h	/
176	Thesis: Conclusion Fixes #53,#61.	rkastl	4897d 16h	/
175	Thesis: Fixes #45.	rkastl	4897d 16h	/
174	Thesis: System integration Fixes #51.	rkastl	4897d 16h	/
173	Thesis: Started with SdController description. Refs #38.	rkastl	4897d 16h	/
172	Thesis: wbclockdomain: refactored and finished. Fixes #39.	rkastl	4897d 16h	/
171	Worked on wishbone part of thesis. Refs #37. Refs #39.	rkastl	4897d 16h	/
170	License rewritten to BSD	rkastl	4897d 16h	/
169	+sdc file for timing analysis	rkastl	4897d 16h	/
168	TbdSd synthesis script reaches timing constraints.	rkastl	4897d 16h	/
167	Read+Modify+Write works on HW + Fixed CRC status token (not mentioned in simplified spec) + Improved TestWbMaster to RMW	rkastl	4897d 16h	/
166	tbTbdSd: fixed	rkastl	4897d 16h	/
165	Only use synchronous high active reset in SDHC-SC-Core.	rkastl	4897d 16h	/
164	Headers updated (LGPL, consistent format)	rkastl	4897d 16h	/
163	Header-Skript supports writing to file and infile replacement.	rkastl	4897d 16h	/
162	Script for generating headers created.	rkastl	4897d 16h	/
161	Verification: CardModel: Check CRC on received data	rkastl	4897d 16h	/