URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 187

Rev	Log message	Author	Age	Path
187	Unit makefiles modified to reflect new location of Makefile.rules.	rkastl	4918d 05h	/
186	Makefile adapted to new paths.	rkastl	4918d 05h	/
185	Restructuring as source repository: Moved sources out of src subdirectory.	rkastl	4918d 05h	/
184	Removed WbSlave shell (refs #69) Moved verification sources to grpSdVerification (fixes #70)	rkastl	4920d 23h	/
183	Removed unneeded wrapper (refs #69) Sector count increased in TestWbMaster (refs #78)	rkastl	4920d 23h	/
182	Fixes #60. Synchronization logic moved to its own unit.	rkastl	4920d 23h	/
181	Refs #60. Fix synthesis with seperate WbClkDomain.	rkastl	4920d 23h	/
180	Moved WbClkDomain to its own unit. Refs #60.	rkastl	4920d 23h	/
179	Fixing build: Added library generation to Makefile.	rkastl	4920d 23h	/
178	Fixed regression: Testbenches did not support synchronous reset.	rkastl	4920d 23h	/
177	Split SdTop into SdClkDomain and SdTop. Refs #60.	rkastl	4920d 23h	/
176	Thesis: Conclusion Fixes #53,#61.	rkastl	4920d 23h	/
175	Thesis: Fixes #45.	rkastl	4920d 23h	/
174	Thesis: System integration Fixes #51.	rkastl	4920d 23h	/
173	Thesis: Started with SdController description. Refs #38.	rkastl	4920d 23h	/
172	Thesis: wbclockdomain: refactored and finished. Fixes #39.	rkastl	4920d 23h	/
171	Worked on wishbone part of thesis. Refs #37. Refs #39.	rkastl	4920d 23h	/
170	License rewritten to BSD	rkastl	4920d 23h	/
169	+sdc file for timing analysis	rkastl	4920d 23h	/
168	TbdSd synthesis script reaches timing constraints.	rkastl	4920d 23h	/