URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

[/] - Rev 80

Rev	Log message	Author	Age	Path
80	Renamed .vhd to .vhdl in last commit.	rkastl	5064d 20h	/
79	Rs232Tx: added to TbdSd TimeoutGenerator: written	rkastl	5064d 20h	/
78	Rs232Tx: implemented, but not tested	rkastl	5064d 20h	/
77	refs #25, synthesis works again	rkastl	5064d 20h	/
76	SdCmd: ioCmd, output registered, fixes #26	rkastl	5064d 20h	/
75	Transfer to SbX, ref #17	rkastl	5064d 20h	/
74	Testbed: All pins, refs #17	rkastl	5064d 20h	/
73	Testbed: Pins.tcl into TbdSdsyn.tcl, refs #17	rkastl	5064d 20h	/
72	TbdSdsyn: +Pins.tcl, refs #17	rkastl	5064d 20h	/
71	Testbed added to synthesis builds	rkastl	5064d 20h	/
70	Testbed: Status leds	rkastl	5064d 20h	/
69	TbdSd synthesis	rkastl	5064d 20h	/
68	Testbed for SD-CORE, refs #17	rkastl	5064d 20h	/
67	IP added	rkastl	5064d 20h	/
66	SdTop: Synthesis works	rkastl	5064d 20h	/
65	SdTop: all sd pins	rkastl	5064d 20h	/
64	SdCommand: Gemeinsamen crc7 verwendet SDController: + voltage checks, refs #15	rkastl	5064d 20h	/
63	SdController: basic init complete	rkastl	5064d 20h	/
62	R2 implemented in complete stack, refs #15.	rkastl	5064d 20h	/
61	Crc: Additional test case	rkastl	5064d 20h	/