URL https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk

Subversion Repositories sdr_ctrl

[/] - Rev 45

Rev	Log message	Author	Age	Path
45	RTL clean up and logic seperation done from sdram bus converter and request generator	dinesha	4501d 10h	/
44	SDRAM data path logic is modified to support 4 command line pipe line of different bank	dinesha	4503d 08h	/
43	Test bench automation to handle differ write/read burst sequence is supported now	dinesha	4503d 10h	/
42	Bug fix in read access is fixed	dinesha	4503d 10h	/
41	Updated Spec ver 0.1 is added back to svn	dinesha	4503d 12h	/
40	Application layer Fifo full conditional are register now to synth timing fixes	dinesha	4504d 05h	/
39	Test Bench upgradation with bigger data burst size	dinesha	4504d 05h	/
38	Port Name clean up	dinesha	4505d 10h	/
37	SDRAM dq and sdram pad clock are termindated inside the top rtl files	dinesha	4505d 11h	/
36	Clean up	dinesha	4506d 02h	/
35	Updated the New Documents - ver 0.1	dinesha	4506d 04h	/
34	Removed the older version	dinesha	4506d 04h	/
33	clean up	dinesha	4506d 04h	/
32	Debug is enable through +define	dinesha	4508d 03h	/
31	Integrated SDRAM controller with wishbone interface is added into SVN	dinesha	4508d 03h	/
30	test bench file for integrated SDRAM controller with wish bone and Standalone SDRAM controller test bench are added into SVN	dinesha	4508d 04h	/
29	SDRAM top and core related run file list are added into svn	dinesha	4508d 04h	/
28	SDRAM top and SDRAM Core Golden files are added into SVN	dinesha	4508d 04h	/
27	Golden log file corresponds the SDRAM core level test case are added into svn	dinesha	4509d 02h	/
26	invalid log files are removed	dinesha	4509d 02h	/