OpenCores
URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

[/] - Rev 15

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
15 - Adding a convenience project for building the testbench.
- Must have ISE 11.1 or higher and project is targeted at device type
xc3s500e-4fg320
- Pinouts may be incorrect for other board types. It is your
responsibility to check. Incorrect pinouts can lead to device damage.		 lynn0p 5357d 09h /
14 Changed the clock period in the DCM generic to match 50mhz lynn0p 5357d 12h /
13 Updated the top level testbench to reflect the fact that you need an
external DCM to run the controller with now.		 lynn0p 5357d 13h /
12 1. rolled write recover clocks back to previous value and edited comments
2. increased 200us wait time to 300us in the init module		 lynn0p 5366d 16h /
11 consolidated capture into one process and added comments lynn0p 5367d 12h /
10 Fixes to more glitches uncovered during testing with my T80 SoC. Some
ops were getting dropped on the floor when the controller needed to do
an auto refresh.		 lynn0p 5367d 16h /
9 Got rid of some redundant busy_n <= '0' statements lynn0p 5369d 04h /
8 Changes made to integrate and test with my homebrew SoC design.

1. One DCM has been removed. Now requires a 100mhz clock fed in. Only
consumes one DCM, if you can find a 100mhz clock somewhere.
2. Small timing modifications to fix memory glitches between controller
and the t80 soft cpu I'm using.		 lynn0p 5369d 05h /
7 Reformatted the comments so they fit in 80 columns lynn0p 5377d 09h /
6 changes to reduce synthesizer warnings, removed unused signals, etc. lynn0p 5377d 14h /
5 added header file for ddr.v lynn0p 5378d 09h /
4 added testbench files to trunk lynn0p 5378d 09h /
3 adding LGPLv3 license file lynn0p 5378d 10h /
2 initial checkin lynn0p 5378d 10h /
1 The project was created and the structure was created root 5378d 13h /

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.