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Rev Log message Author Age Path
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7027d 05h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7027d 08h /
17 Initial Checkin arif_endro 7035d 05h /
16 Changes constan and minor fix arif_endro 7038d 08h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7041d 06h /
14 *** empty log message *** arif_endro 7046d 04h /
13 Update License arif_endro 7057d 05h /
12 Update License
Change reset signal handle
arif_endro 7057d 05h /
11 Update License
Change reset signal handle
arif_endro 7057d 05h /
10 Added script for generating cos ROM. arif_endro 7067d 08h /
9 Added documentation arif_endro 7084d 07h /
8 This commit was manufactured by cvs2svn to create tag 'okinawa_1'. 7098d 08h /
7 To view chipscope exported output using ModelSim waveform window arif_endro 7098d 08h /
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7099d 09h /
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7099d 09h /
4 Fix elsif and if statement arif_endro 7102d 03h /
3 This commit was manufactured by cvs2svn to create tag 'VSFR_1'. 7105d 10h /
2 Initial releases arif_endro 7105d 10h /
1 Standard project directories initialized by cvs2svn. 7105d 10h /

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