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Rev Log message Author Age Path
23 Disable clear signal. arif_endro 5841d 07h /
22 Update last bit output assignment method. arif_endro 5841d 07h /
21 This commit was manufactured by cvs2svn to create tag 'version_1_1'. 7026d 08h /
20 New Version arif_endro 7026d 08h /
19 Screen shot from chipscope analyzer view, this is how this design work. arif_endro 7032d 07h /
18 This bit files generates better wave than previous (i.e. more smooth) arif_endro 7032d 09h /
17 Initial Checkin arif_endro 7040d 06h /
16 Changes constan and minor fix arif_endro 7043d 09h /
15 Xilinx FPGA XC2V2000 bit files the first version. arif_endro 7046d 07h /
14 *** empty log message *** arif_endro 7051d 05h /
13 Update License arif_endro 7062d 06h /
12 Update License
Change reset signal handle
arif_endro 7062d 07h /
11 Update License
Change reset signal handle
arif_endro 7062d 07h /
10 Added script for generating cos ROM. arif_endro 7072d 09h /
9 Added documentation arif_endro 7089d 08h /
8 This commit was manufactured by cvs2svn to create tag 'okinawa_1'. 7103d 09h /
7 To view chipscope exported output using ModelSim waveform window arif_endro 7103d 09h /
6 Added Xilinx FPGA implementation (e.g. connector to ILA, ICON, and VIO) arif_endro 7104d 11h /
5 Added interface in/out and testing paralelly (e.g. square and triangular) arif_endro 7104d 11h /
4 Fix elsif and if statement arif_endro 7107d 04h /

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