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Rev Log message Author Age Path
104 fixed search in preprocessor script
added initial orp_soc project
jt_eaton 4501d 16h /
103 added user guide
resynced to local repository
jt_eaton 4521d 16h /
102 all ip-xact files now readable by kactus2 jt_eaton 4583d 12h /
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT
jt_eaton 4584d 13h /
100 created workspace prroject=fpga_mrisc for single compile
general cleanup
jt_eaton 4596d 21h /
99 moved all projects into /projects/opencores.org
added build_register
added fizzim
jt_eaton 4639d 14h /
98 removed unneeded sim jt_eaton 4675d 17h /
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims
jt_eaton 4675d 19h /
96 hierConnections now create ports jt_eaton 4749d 15h /
95 added first cut at busdefs
added clock reset enable pads and jtag_rpc
jt_eaton 4758d 13h /
94 socgen now supports both sim and syn views
now allow each xml file to set its destination
jt_eaton 4785d 14h /
93 build scripts now support model views
linting and coverage starting to work again
jt_eaton 4798d 02h /
92 all testbenchs now built from /sim/xml files
bench /models now in Testbench
jt_eaton 4803d 03h /
91 fixed all sims, coverage not working jt_eaton 4810d 22h /
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4811d 14h /
89 removed unneeded debug directories jt_eaton 4832d 22h /
88 added xml files for test benches
added gEDA sym sch starter templates
jt_eaton 4832d 22h /
87 removed prebuilt geda schematics and symbols jt_eaton 4843d 15h /
86 split out all fpgas into families
added fpga pad_ring level
jt_eaton 4851d 12h /
85 moved all synthesis into fpgas lib
fixed memory leak in recursive routines
jt_eaton 4858d 11h /

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