URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 31

Rev	Log message	Author	Age	Path
31	split T6502_fsm out into smaller blocks	jt_eaton	5151d 07h	/
30	split out fsm code into seperate modules fixed bugs so that prog_test passes	jt_eaton	5153d 16h	/
29	removed old files	jt_eaton	5156d 15h	/
28	added T6502 processor added vga_char_ctrl	jt_eaton	5156d 15h	/
27	added uart and ps2 host and models added more documentation	jt_eaton	5178d 05h	/
26	moved install instructions from doc -> tools added scripts to install or32 gnu toolchain and fizzim state tool	jt_eaton	5186d 18h	/
25	updated for ubuntu 10.4 install	jt_eaton	5187d 10h	/
24	moved to docs	jt_eaton	5188d 13h	/
23	fixed typos and ommisions	jt_eaton	5188d 13h	/
22	added install instructions for ubuntu 10.4	jt_eaton	5188d 14h	/
21	now use serial_rcvr	jt_eaton	5189d 03h	/
20	added Nexys2 support expanded docs created tools directory	jt_eaton	5189d 03h	/
19	added serial_xmit module updated and added docs	jt_eaton	5196d 09h	/
18	added geda support files and docs	jt_eaton	5201d 08h	/
17	removed old doc files	jt_eaton	5203d 09h	/
16	added geda scripts and symbols/sch	jt_eaton	5203d 09h	/
15	added io_module with ps2 and uart added soc_mouse with uart and mouse interface fixed latch in mrisc	jt_eaton	5209d 12h	/
14	add web_uploads	jt_eaton	5219d 16h	/
13	updated for xilinx webpack 11.1	jt_eaton	5227d 06h	/
12	switched Makefile to use xilinx 11.1 ise removed timescale from synthesis files now use consist timescale header in all sims	jt_eaton	5227d 17h	/