URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 63

Rev	Log message	Author	Age	Path
63	added install config for Ubuntu 10.10	jt_eaton	5068d 19h	/
62	fixed parameters from `defines	jt_eaton	5072d 11h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5072d 13h	/
60	moved alu_logic into seperate component	jt_eaton	5073d 00h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5073d 00h	/
58	removed old Makefiles	jt_eaton	5073d 15h	/
57	Now generate all filelists from xml files	jt_eaton	5073d 16h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5079d 00h	/
55	removed pre-rout and gates sims	jt_eaton	5081d 20h	/
54	now set up fpga targets from xml files	jt_eaton	5081d 22h	/
53	fixed check_fpgas	jt_eaton	5084d 11h	/
52	removed noworking sims and syn	jt_eaton	5084d 12h	/
51	removed old test	jt_eaton	5084d 12h	/
50	clean up from last checkin	jt_eaton	5084d 12h	/
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5084d 15h	/
48	added support for covered code checking	jt_eaton	5106d 21h	/
47	removed old variant	jt_eaton	5121d 00h	/
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5121d 00h	/
45	added 6502 sims/software and synth	jt_eaton	5127d 20h	/
44	added new parts and sw for 6502	jt_eaton	5127d 23h	/