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Rev Log message Author Age Path
68 moved to seperate components jt_eaton 5027d 21h /
67 updated installs jt_eaton 5027d 21h /
66 converted sims to use parameters
added msp and 6502 software installs
jt_eaton 5028d 20h /
65 added params.sim to sims
updated install's
jt_eaton 5033d 21h /
64 added support for Fedora 13 jt_eaton 5037d 19h /
63 added install config for Ubuntu 10.10 jt_eaton 5038d 02h /
62 fixed parameters from `defines jt_eaton 5041d 18h /
61 now generate dut files for coverage
removed use of lndir
jt_eaton 5041d 20h /
60 moved alu_logic into seperate component jt_eaton 5042d 07h /
59 added filelist.core to syn dirs to customize core jt_eaton 5042d 07h /
58 removed old Makefiles jt_eaton 5042d 22h /
57 Now generate all filelists from xml files jt_eaton 5042d 23h /
56 soc_builder now builds verilog from xml files jt_eaton 5048d 07h /
55 removed pre-rout and gates sims jt_eaton 5051d 03h /
54 now set up fpga targets from xml files jt_eaton 5051d 04h /
53 fixed check_fpgas jt_eaton 5053d 18h /
52 removed noworking sims and syn jt_eaton 5053d 18h /
51 removed old test jt_eaton 5053d 19h /
50 clean up from last checkin jt_eaton 5053d 19h /
49 added covered code coverage
added xml descriptors
added soc_Link tool
jt_eaton 5053d 22h /

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