URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 70

Rev	Log message	Author	Age	Path
70	ignore work	jt_eaton	5007d 00h	/
69	added work dir	jt_eaton	5007d 00h	/
68	moved to seperate components	jt_eaton	5010d 00h	/
67	updated installs	jt_eaton	5010d 00h	/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5011d 00h	/
65	added params.sim to sims updated install's	jt_eaton	5016d 00h	/
64	added support for Fedora 13	jt_eaton	5019d 23h	/
63	added install config for Ubuntu 10.10	jt_eaton	5020d 06h	/
62	fixed parameters from `defines	jt_eaton	5023d 22h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5023d 23h	/
60	moved alu_logic into seperate component	jt_eaton	5024d 11h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5024d 11h	/
58	removed old Makefiles	jt_eaton	5025d 02h	/
57	Now generate all filelists from xml files	jt_eaton	5025d 02h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5030d 11h	/
55	removed pre-rout and gates sims	jt_eaton	5033d 07h	/
54	now set up fpga targets from xml files	jt_eaton	5033d 08h	/
53	fixed check_fpgas	jt_eaton	5035d 21h	/
52	removed noworking sims and syn	jt_eaton	5035d 22h	/
51	removed old test	jt_eaton	5035d 22h	/