URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 75

Rev	Log message	Author	Age	Path
75	added linting using verilator	jt_eaton	4986d 21h	/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	4992d 02h	/
73	removed dup png files	jt_eaton	5000d 02h	/
72	split T6502 into components moved io_module into seperate project removed liblists direct loads filelists for sims and coverage add hier type into xml files to generate verilog	jt_eaton	5000d 04h	/
71	ignore anything in work	jt_eaton	5006d 20h	/
70	ignore work	jt_eaton	5006d 20h	/
69	added work dir	jt_eaton	5006d 21h	/
68	moved to seperate components	jt_eaton	5009d 20h	/
67	updated installs	jt_eaton	5009d 20h	/
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5010d 20h	/
65	added params.sim to sims updated install's	jt_eaton	5015d 20h	/
64	added support for Fedora 13	jt_eaton	5019d 19h	/
63	added install config for Ubuntu 10.10	jt_eaton	5020d 02h	/
62	fixed parameters from `defines	jt_eaton	5023d 18h	/
61	now generate dut files for coverage removed use of lndir	jt_eaton	5023d 19h	/
60	moved alu_logic into seperate component	jt_eaton	5024d 07h	/
59	added filelist.core to syn dirs to customize core	jt_eaton	5024d 07h	/
58	removed old Makefiles	jt_eaton	5024d 22h	/
57	Now generate all filelists from xml files	jt_eaton	5024d 22h	/
56	soc_builder now builds verilog from xml files	jt_eaton	5030d 07h	/