URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 93

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Rev	Log message	Author	Age	Path
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4809d 14h	/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4814d 15h	/
91	fixed all sims, coverage not working	jt_eaton	4822d 10h	/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4823d 02h	/
89	removed unneeded debug directories	jt_eaton	4844d 10h	/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4844d 11h	/
87	removed prebuilt geda schematics and symbols	jt_eaton	4855d 03h	/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4863d 00h	/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4869d 23h	/
84	removed unneeded files	jt_eaton	4920d 05h	/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4920d 09h	/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4935d 03h	/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4956d 09h	/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4986d 00h	/
79	removed unsupported code	jt_eaton	4992d 05h	/
78	removed unsupported fpga	jt_eaton	4992d 05h	/
77	now generate syn and cov Makefiles leave log and out files in sim/run directory	jt_eaton	4992d 05h	/
76	added wave.save files now generate sims Makefile and params.sim leave sim log and vcd files in sim/run/directory	jt_eaton	4994d 11h	/
75	added linting using verilator	jt_eaton	4998d 03h	/
74	split out sw Makefile into projects /bin split out _cpu into seperate component	jt_eaton	5003d 08h	/

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Subversion Repositories socgen

[/] - Rev 93

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