URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] - Rev 99

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Rev	Log message	Author	Age	Path
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4657d 00h	/
98	removed unneeded sim	jt_eaton	4693d 04h	/
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4693d 05h	/
96	hierConnections now create ports	jt_eaton	4767d 02h	/
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4775d 23h	/
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4803d 01h	/
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4815d 13h	/
92	all testbenchs now built from /sim/xml files bench /models now in Testbench	jt_eaton	4820d 14h	/
91	fixed all sims, coverage not working	jt_eaton	4828d 09h	/
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4829d 01h	/
89	removed unneeded debug directories	jt_eaton	4850d 09h	/
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4850d 09h	/
87	removed prebuilt geda schematics and symbols	jt_eaton	4861d 02h	/
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4868d 23h	/
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4875d 22h	/
84	removed unneeded files	jt_eaton	4926d 03h	/
83	added design.soc files xml files now 99% 1685 complient	jt_eaton	4926d 07h	/
82	renmamed cde_synchronizers to cde_sync added hierarchial dependency search converted more xmp to follow ip-xact	jt_eaton	4941d 01h	/
81	morphing xml files to use 1685 removed log directories	jt_eaton	4962d 08h	/
80	now generate all sims and syns param and filelists for xml	jt_eaton	4991d 23h	/

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Subversion Repositories socgen

[/] - Rev 99

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