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Subversion Repositories spdif_interface

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Rev Log message Author Age Path
42 Fixed bug with lock event generation. gedra 7296d 19h /
41 Test bench update. gedra 7296d 19h /
40 Improved test bench. gedra 7297d 20h /
39 Bug-fix. gedra 7297d 20h /
38 Signal renaming and bug fix. gedra 7311d 20h /
37 Converted to numeric_std and fixed a few bugs. gedra 7312d 22h /
36 Top level entity for receiver. gedra 7312d 22h /
35 Top level test bench for receiver. NB! Not complete. gedra 7312d 22h /
34 Converter to numeric_std and added hex functions gedra 7312d 22h /
33 Minor update. gedra 7312d 22h /
32 Wishbone bus utilities. gedra 7314d 17h /
31 Added data output. gedra 7314d 17h /
30 Added Wishbone bus cycle decoder. gedra 7315d 18h /
29 Wishbone bus cycle decoder. gedra 7315d 18h /
28 Delint'ed and changed name of architecture. gedra 7320d 02h /
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7320d 18h /
26 Fixed a few bugs. gedra 7322d 17h /
25 Changed status reg. declaration gedra 7322d 17h /
24 Added channel status decoding. gedra 7322d 17h /
23 Added frame decoder gedra 7322d 17h /

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