URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] - Rev 44

Rev	Log message	Author	Age	Path
44	Transmitter Wishbone bus cycle decoder.	gedra	7288d 00h	/
43	This commit was manufactured by cvs2svn to create tag 'rx_beta_1'.		7289d 02h	/
42	Fixed bug with lock event generation.	gedra	7289d 02h	/
41	Test bench update.	gedra	7289d 02h	/
40	Improved test bench.	gedra	7290d 02h	/
39	Bug-fix.	gedra	7290d 02h	/
38	Signal renaming and bug fix.	gedra	7304d 03h	/
37	Converted to numeric_std and fixed a few bugs.	gedra	7305d 05h	/
36	Top level entity for receiver.	gedra	7305d 05h	/
35	Top level test bench for receiver. NB! Not complete.	gedra	7305d 05h	/
34	Converter to numeric_std and added hex functions	gedra	7305d 05h	/
33	Minor update.	gedra	7305d 05h	/
32	Wishbone bus utilities.	gedra	7306d 23h	/
31	Added data output.	gedra	7306d 23h	/
30	Added Wishbone bus cycle decoder.	gedra	7308d 01h	/
29	Wishbone bus cycle decoder.	gedra	7308d 01h	/
28	Delint'ed and changed name of architecture.	gedra	7312d 09h	/
27	Alternate dual port memory implementation for Altera FPGA's.	gedra	7313d 00h	/
26	Fixed a few bugs.	gedra	7315d 00h	/
25	Changed status reg. declaration	gedra	7315d 00h	/