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Rev Log message Author Age Path
13 Fixed FIFO Full condition for large fifo, added separate
tests to example bridge
ghutchis 5253d 07h /
12 Added absolute priority arbitration to ring to avoid
having two ring taps transmit at same time
ghutchis 5254d 06h /
11 Updated bridge example to fix a number of small bugs.
First packet now exits bridge from all ports.
ghutchis 5255d 05h /
10 Fixed "locked" variable in rrslow ghutchis 5255d 10h /
9 Added rx_gigmac, additional debug work on concentrator & fib ghutchis 5255d 10h /
8 Added compiling version of bridge example ghutchis 5256d 22h /
7 Added rrslow ghutchis 5259d 02h /
6 Modified "B" output buffer for full-rate operation ghutchis 5261d 10h /
5 Added new component for port ring ghutchis 5262d 02h /
4 Added example directory with basic bridge ghutchis 5262d 21h /
3 Added small/synchronizer FIFO, along with minimal testbench ghutchis 5263d 20h /
2 Initial commit of directory structure and basic components ghutchis 5268d 05h /
1 The project and the structure was created root 5275d 21h /

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