URL https://opencores.org/ocsvn/storm_core/storm_core/trunk

Subversion Repositories storm_core

[/] - Rev 16

Rev	Log message	Author	Age	Path
16	WB_TGC(5) signal fixed (indicating instruction/data fetch), coprocessor read-access bug fixed	zero_gravity	4526d 06h	/
15	new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;)	zero_gravity	4526d 11h	/
14	- corrected stupid error in access arbiter - updated minor issues	zero_gravity	4664d 07h	/
13	- corrected endianess converter for memory access - corrected error in temporal dependence detector	zero_gravity	4665d 03h	/
12	- corrected error in memory write back interface - corrected immediate/register offset for byte/halfword memory access	zero_gravity	4665d 08h	/
11		zero_gravity	4668d 12h	/
10	New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface. Ready to execute assembled ARM ASM code, arm-elf-assembler included.	zero_gravity	4668d 12h	/
9	documentation updated	zero_gravity	4758d 10h	/
8	documentation uploaded ;)	zero_gravity	4760d 04h	/
7	- new register file architecture - fixed multi-cycle op bug - architecture update	zero_gravity	4764d 03h	/
6	new core version - now with arm compatible memory interface	zero_gravity	4770d 03h	/
5	memory interface updated	zero_gravity	4821d 02h	/
4	new instruction cycle controller - interrupt call bug seems to be fixed	zero_gravity	4823d 04h	/
3		zero_gravity	4824d 11h	/
2		zero_gravity	4836d 12h	/
1	The project and the structure was created	root	4839d 19h	/