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Rev Log message Author Age Path
20 - update of data sheet -> note for system memory map layout and d-cache configuration zero_gravity 4518d 22h /
19 - simulation test bench added
- example for compatible wishbone fabric/SoC added
- block transfers from user bank updated		 zero_gravity 4519d 02h /
18 makefile update to ensure no thumb code is generated zero_gravity 4524d 06h /
17 small synthesis-friendly update of memory components zero_gravity 4527d 00h /
16 WB_TGC(5) signal fixed (indicating instruction/data fetch),
coprocessor read-access bug fixed		 zero_gravity 4527d 02h /
15 new core version! pipelined wishbone interface, I/D-cache, internal processor timer/lfsr, block transfer instructions, system mode, ... ;) zero_gravity 4527d 06h /
14 - corrected stupid error in access arbiter
- updated minor issues		 zero_gravity 4665d 03h /
13 - corrected endianess converter for memory access
- corrected error in temporal dependence detector		 zero_gravity 4665d 22h /
12 - corrected error in memory write back interface
- corrected immediate/register offset for byte/halfword memory access		 zero_gravity 4666d 04h /
11 zero_gravity 4669d 08h /
10 New CORE version, ncluding complete system setup with inbuilt memory and wishbone interface.
Ready to execute assembled ARM ASM code, arm-elf-assembler included.		 zero_gravity 4669d 08h /
9 documentation updated zero_gravity 4759d 06h /
8 documentation uploaded ;) zero_gravity 4761d 00h /
7 - new register file architecture
- fixed multi-cycle op bug
- architecture update		 zero_gravity 4764d 22h /
6 new core version - now with arm compatible memory interface zero_gravity 4770d 23h /
5 memory interface updated zero_gravity 4821d 21h /
4 new instruction cycle controller - interrupt call bug seems to be fixed zero_gravity 4824d 00h /
3 zero_gravity 4825d 07h /
2 zero_gravity 4837d 07h /
1 The project and the structure was created root 4840d 14h /

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