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[/] - Rev 51

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Rev	Log message	Author	Age	Path
51	Rewrote verilog for write enable signals for different destinations in the last stage. The code is much easier to read and more liner to follow.	samg	8219d 15h	/
50	fixed sensitivity list error in last pipeline stage	samg	8220d 03h	/
49	changed run script name and added instructions	samg	8220d 03h	/
48	fixed neg edge event trigger	samg	8220d 04h	/
47	changed prefix from ~\| to ! (same thing)	samg	8220d 04h	/
46	vcd dumpvar captures all levels	samg	8222d 14h	/
45	Fixed bug in 16 bit data swap instruction. The instructions were making the regf status module look at reg 0 even though reg 0 didn't have anything to do with the purpose of the instruction. Made reg b addr field mirror reg a field. This error caused unecessary stalls. Performance increase caused by calling instruction correctly and not causing stalls from mal-formed instructions.	samg	8222d 14h	/
44	- Removed #1 delay (was originally put in for debug) - Stall signal forced low during pipeline flush. (No effect on functionality but it is easier to look at the waveforms during debug)	samg	8222d 14h	/
43	integrated common rams into processor	samg	8246d 09h	/
42	minor header correction	samg	8246d 09h	/
41	common rams	samg	8246d 09h	/
40	added header and parameter restructure	samg	8246d 09h	/
39	added header and restructured parameters	samg	8246d 09h	/
38	minor header fix	samg	8246d 09h	/
37	added header and modified parameter structure	samg	8246d 09h	/
36	integrated common memories	samg	8246d 09h	/
35	integrated standard memories and added header	samg	8246d 10h	/
34	Used common header	samg	8248d 13h	/
33	SXP Documentation	samg	8253d 18h	/
32	timer controller for processor	samg	8257d 03h	/

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[/] - Rev 51

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