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Rev Log message Author Age Path
8 Indented jcastillo 7378d 09h /
7 Removed (I dont know why I upload it) jcastillo 7385d 08h /
6 Used indent command on C code jcastillo 7385d 08h /
5 Add timescale directive jcastillo 7399d 16h /
4 Corrected load signal delay.
Now the simulation works in Icarus, Aldec, NCVerilog and ModelSim
jcastillo 7424d 17h /
3 This commit was manufactured by cvs2svn to create tag 'V10'. 7441d 08h /
2 First import jcastillo 7441d 08h /
1 Standard project directories initialized by cvs2svn. 7441d 08h /

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