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Rev Log message Author Age Path
27 connect missing input direction for IO G arniml 6630d 06h /
26 fix org for page 11 in COP420 code arniml 6630d 06h /
25 fix wrong aisc commands arniml 6630d 07h /
24 finalize test arniml 6630d 07h /
23 finalize test arniml 6630d 22h /
22 finish test arniml 6631d 07h /
21 include t420 system and testbench arniml 6631d 08h /
20 initial check-in arniml 6631d 08h /
19 moved elements to separate design unit tb_elems arniml 6631d 08h /
18 initial check-in arniml 6631d 08h /
17 remove direct specification of cpu type arniml 6632d 08h /
16 enabled t420 support arniml 6632d 08h /
15 initial check-in arniml 6632d 08h /
14 t420 hierarchies added arniml 6632d 08h /
13 hand-down clock divider option arniml 6639d 04h /
12 fix sensitivity list arniml 6640d 04h /
11 renamed to rtl arniml 6640d 04h /
10 renamed t400_por configuration to rtl arniml 6640d 04h /
9 initial check-in arniml 6640d 05h /
8 phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o arniml 6640d 17h /

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