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Rev Log message Author Age Path
76 remove tb_int_behav_c0 arniml 6591d 22h /
75 initial check-in arniml 6591d 22h /
74 add interrupt testbench and 'int' test class arniml 6592d 02h /
73 use 'after' instead of wait for signal delay
should resolve problems with delta cycle arrival times
arniml 6592d 02h /
72 make test start more robust regarding timing arniml 6592d 02h /
71 obsolete arniml 6592d 06h /
70 interrupt functionality added arniml 6592d 06h /
69 instrument testbench arniml 6592d 06h /
68 updates for interrupt support arniml 6592d 06h /
67 explicitly select clock divider 4 arniml 6592d 06h /
66 explicitly select clock divider 8 arniml 6592d 06h /
65 add global signals for testbench instrumentation arniml 6592d 06h /
64 add fail reporting for port d arniml 6592d 06h /
63 initial check-in arniml 6592d 06h /
62 int target added arniml 6592d 06h /
61 initial check-in arniml 6594d 09h /
60 connect cko_i to bit 2 of IN bus arniml 6596d 00h /
59 check CKO in general purpose configuration arniml 6596d 00h /
58 consider IN port arniml 6597d 00h /
57 consider CKO and IN port arniml 6597d 00h /

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