OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 129

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
129 cleanup copyright notice arniml 7309d 22h /
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7317d 02h /
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7317d 03h /
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7317d 03h /
125 exclude from dump compare arniml 7317d 03h /
124 fix wrong handling of MB after return from interrupt arniml 7318d 01h /
123 support hex file for external ROM arniml 7318d 01h /
122 test MB after return from interrupt arniml 7318d 01h /
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7320d 18h /
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7320d 18h /
119 add int_in_progress_o to entity of int module arniml 7320d 18h /
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7320d 18h /
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7321d 19h /
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7349d 19h /
115 extend description arniml 7350d 23h /
114 initial check-in arniml 7354d 19h /
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7361d 04h /
112 update tb_behav_c0 for new ROM layout arniml 7361d 04h /
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7361d 04h /
110 exchange syn_rom for lpm_rom arniml 7361d 04h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.