URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 148

Rev	Log message	Author	Age	Path
148	initial check-in	arniml	7168d 01h	/
147	initial check-in for release 0.5 BETA	arniml	7204d 03h	/
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7205d 03h	/
145	remove PROG and end of XTAL2, see comment for details	arniml	7205d 04h	/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7205d 04h	/
143	Fix bug report: "RD' and WR' not asserted for INS A, BUS and OUTL BUS, A" rd is asserted for INS A, BUS wr is asserted for OUTL BUS, A P1, P2 and BUS are written in first instruction cycle	arniml	7205d 05h	/
142	deassert rd_q, wr_q and prog_q at end of XTAL3	arniml	7205d 05h	/
141	disable external memory to avoid conflicts with outl a, bus	arniml	7205d 05h	/
140	remove tAW sanity check conflicts with OUTL A, BUS	arniml	7205d 05h	/
139	add bug P1 constantly in push-pull mode in t8048	arniml	7206d 15h	/
138	Fix for: P1 constantly in push-pull mode in t8048	arniml	7206d 15h	/
137	add link to COMPILE_LIST	arniml	7244d 04h	/
136	initial check-in	arniml	7244d 04h	/
135	add bug PSENn Timing	arniml	7248d 14h	/
134	Fix bug report: "PSENn Timing" PSEN is now only asserted for the second cycle if explicitely requested by assert_psen_s. The previous implementation asserted PSEN together with RD or WR.	arniml	7249d 00h	/
133	add checks for PSEN	arniml	7249d 00h	/
132	stop simulation upon assertion error	arniml	7249d 00h	/
131	update	arniml	7249d 00h	/
130	initial check-in	arniml	7249d 00h	/
129	cleanup copyright notice	arniml	7311d 08h	/