URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 163

Rev	Log message	Author	Age	Path
163	add bug Wrong clock applied to T0	arniml	6996d 10h	/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	6996d 10h	/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7027d 14h	/
160	add others to case statement	arniml	7148d 10h	/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7148d 10h	/
158	added hierarchies t8039_notri and t8048_notri	arniml	7148d 10h	/
157	removed obsolete constant	arniml	7148d 11h	/
156	added hierarchy t8039_notri	arniml	7148d 11h	/
155	initial check-in	arniml	7148d 11h	/
154	added t8039_notri hierarchy	arniml	7148d 11h	/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7149d 08h	/
152	added hierarchy t8048_notri and system components package	arniml	7149d 23h	/
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7149d 23h	/
150	intruduced hierarchy t8048_notri where all system functionality except bidirectional ports is handled	arniml	7150d 07h	/
149	update	arniml	7150d 07h	/
148	initial check-in	arniml	7150d 07h	/
147	initial check-in for release 0.5 BETA	arniml	7186d 09h	/
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7187d 09h	/
145	remove PROG and end of XTAL2, see comment for details	arniml	7187d 10h	/
144	delay db_dir_o by one machine cycle this fixes the timing relation between BUS data and WR'	arniml	7187d 10h	/