URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 172

Rev	Log message	Author	Age	Path
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	6989d 18h	/
171	remove obsolete output stack_high_o	arniml	6990d 18h	/
170	intermediate update	arniml	6992d 01h	/
169	initial check-in	arniml	6992d 06h	/
168	change address range of wb_master	arniml	6992d 06h	/
167	simplify address range: - configuration range - Wishbone range	arniml	6992d 06h	/
166	assign default for state_s	arniml	6993d 22h	/
165	add component wb_master.vhd	arniml	6994d 21h	/
164	initial check-in	arniml	6994d 21h	/
163	add bug Wrong clock applied to T0	arniml	6995d 20h	/
162	Fix bug report: "Wrong clock applied to T0" t0_o is generated inside clock_ctrl with a separate flip-flop running with xtal_i	arniml	6995d 20h	/
161	fix syntax problem that triggers an error with GHDL 0.18	arniml	7027d 00h	/
160	add others to case statement	arniml	7147d 20h	/
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7147d 21h	/
158	added hierarchies t8039_notri and t8048_notri	arniml	7147d 21h	/
157	removed obsolete constant	arniml	7147d 21h	/
156	added hierarchy t8039_notri	arniml	7147d 21h	/
155	initial check-in	arniml	7147d 21h	/
154	added t8039_notri hierarchy	arniml	7147d 21h	/
153	introduced generic gate_port_input_g forces masking of P1 and P2 input bus	arniml	7148d 18h	/