OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 193

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
193 iManual arniml 6848d 19h /
192 update list for Wishbone toplevel arniml 6849d 06h /
191 preliminary version 0.2 arniml 6849d 10h /
190 finalize change log for release 0.6 beta arniml 6850d 04h /
189 add bug report
"Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"
arniml 6881d 06h /
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch
arniml 6881d 06h /
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag
arniml 6881d 07h /
186 update to version 0.2 arniml 6882d 08h /
185 initial check-in arniml 6887d 06h /
184 initial check-in arniml 6887d 07h /
183 fix missing assignment to outclock arniml 6887d 10h /
182 intermediate version arniml 6967d 09h /
181 fix typo arniml 6967d 12h /
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6975d 17h /
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6975d 17h /
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'
arniml 6977d 05h /
177 Implement db_dir_o glitch-safe arniml 6977d 05h /
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).
arniml 6977d 05h /
175 add bug report
"MSB of Program Counter changed upon PC increment"
arniml 6978d 08h /
174 fix bug report
"MSB of Program Counter changed upon PC increment"
arniml 6978d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.