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Rev Log message Author Age Path
288 updates for release 1.1 arniml 5893d 20h /
287 add notes on FPGA implementation arniml 5893d 20h /
286 hierarchy update, RAM and ROM clarification arniml 5893d 20h /
285 generate D for synchronous implementation in clocked process arniml 5894d 21h /
284 better support for ISE/XST:
opc_table and opc_decoder merged into decoder_pack and decoder
arniml 5894d 21h /
283 update to new mnemonic decoder arniml 5894d 22h /
282 decouple bidir port T0 from P1
fixes testcase black_box/tx/t0
arniml 5895d 21h /
281 clarify testcase compilation arniml 5895d 21h /
280 added syn directory structure arniml 5896d 20h /
279 update arniml 5911d 19h /
278 initial check-in arniml 5911d 21h /
277 This commit was manufactured by cvs2svn to create tag 'rel_1_0'. 6392d 19h /
276 add change notes for release 1.0 arniml 6392d 19h /
275 fix sensitivity list arniml 6393d 17h /
274 revision 1.0 arniml 6393d 18h /
273 reset counter_q arniml 6411d 04h /
272 fix entity port names arniml 6415d 06h /
271 initial check-in arniml 6415d 06h /
270 fix component name arniml 6415d 07h /
269 update list for inclusion of t8243 testbenches arniml 6542d 19h /

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