URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 72

Rev	Log message	Author	Age	Path
72	removed superfluous signal from sensitivity list	arniml	7404d 12h	/
71	add T8039 and its testbench	arniml	7410d 04h	/
70	clean test cell before make	arniml	7410d 04h	/
69	fix name of istrobe	arniml	7410d 04h	/
68	connect T0 and T1 to P1	arniml	7410d 04h	/
67	initial check-in	arniml	7410d 04h	/
66	add temporary workaround for GHDL 0.11	arniml	7410d 04h	/
65	clean up sensitivity list	arniml	7410d 04h	/
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7410d 04h	/
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7410d 04h	/
62	initial check-in	arniml	7410d 04h	/
61	expand script for dump compare	arniml	7412d 01h	/
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7413d 01h	/
59	increment prescaler with MSTATE4	arniml	7413d 01h	/
58	add periodic interrupt	arniml	7413d 01h	/
57	abort if no interrupt occurs	arniml	7413d 01h	/
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7414d 02h	/
55	add dependency to tb_behav_pack for decoder	arniml	7414d 02h	/
54	- add tb_istrobe_s	arniml	7414d 02h	/
53	make istrobe visible through testbench package	arniml	7414d 02h	/