OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] - Rev 92

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
92 work around bug in Quartus II 4.0 arniml 7455d 14h /
91 fix edge detector bug for counter arniml 7455d 14h /
90 intial check-in arniml 7455d 14h /
89 initial check-in arniml 7469d 11h /
88 allow memory bank switching during interrupts arniml 7470d 13h /
87 abort gracfullt if memory bank switching does not work arniml 7470d 13h /
86 update notice about expander port instructions arniml 7470d 18h /
85 initial check-in arniml 7470d 18h /
84 add if_timing module arniml 7476d 09h /
83 connect if_timing to P2 output of T48 arniml 7476d 09h /
82 check expander timings arniml 7476d 09h /
81 initial check-in arniml 7476d 13h /
80 added if_timing arniml 7476d 13h /
79 add if_timing module arniml 7476d 13h /
78 adjust external timing of BUS arniml 7476d 13h /
77 move from std_logic_arith to numeric_std arniml 7477d 06h /
76 initial check-in arniml 7477d 10h /
75 remove obsolete design unit arniml 7477d 10h /
74 enhance pass/fail detection arniml 7477d 18h /
73 removed dummy_s - workaround not longer needed for GHDL 0.11.1 arniml 7477d 18h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.